Explain programmable interrupt controller 8259A in detail

Subject: Microprocessor and Interfacing
Semester: BE Computer Sem-5
Question: programmable interrupt controller 8259A

Answer :


The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for use with the 8085 and 8086 microprocessors.

The 8259 can be used for applications that use more than five numbers of interrupts from multiple sources.

The main features of 8259 are listed below
Manage eight levels of interrupts.

Eight interrupts are spaced at the interval of four or eight locations.

Resolve eight levels of priority in fully nested mode, automatic rotation mode or specific rotation mode.

Mask each interrupt individually.

Read the status of pending interrupt, in-service interrupt, and masked interrupt.

Accept either the level triggered or edge triggered interrupt

8259 Internal Block Diagram
Explain programmable interrupt controller 8259A in detail


Read/Write Logic
It is typical R/W logic.

When address line A0 is at logic 0, the controller is selected to write a command word or read status.

The Chip Select logic and A0 determine the port address of controller.


Control Logic
It has two pins: INT as output and INTA as input.

The INT is connected to INTR pin of MPU


Interrupt Registers and Priority Resolver
    1. Interrupt Request Register (IRR)
    2. Interrupt In-Service Register (ISR)
    3. Priority Resolver
    4. Interrupt Mask Register (IMR)


Interrupt Request Register (IRR) and Interrupt In-Service Register (ISR)
Interrupt input lines are handled by two registers in cascade – IRR and ISR

IRR is used to store all interrupt which are requesting service.

ISR is used to store all interrupts which are being serviced.
 

Priority Resolver
This logic block determines the priorities of the bit set in IRR.

IR0 is having highest priority, IR7 is having lowest priority

Interrupt Mask Register
It stores bits which mask the interrupt lines to be masked

IMR operates on the IRR.

Masking of high priority input will not affect the interrupt request lines.

Cascade Buffer / Comparator
This block is used to expand the number of interrupt levels by cascading two or more 8259As.
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