Semester: BE Computer Sem-5
Question: Architecture of Pentium processor
Answer :
Bus Unit :
Give physical interface between processor & external world using address , data & control bus.
It support pipelining.
Code Cache :
Internal code cache is 8kb memory organized as two way set associative cache with a line size of 32 byte.
Instruction which will be supplied to the processor execution pipelines.
Data Cache :
Internal data cache is 8kb memory organized as two way set associative cache with a line size of 32 byte.
Instruction which will be supplied to the processor execution unnit.
Prefetcher :
Bus cycle used by prefetcher to fill the cache.
Prefetcher can also access two lines to get data which resides partially in two separate lines within the cache.
Prefetch Buffer :
Pentium consists of 4 prefetch buffers as 2 independent pairs.
Instruction take from 1 cache & placed in one of pairs & other pair remain idle.
Other pair comes into the picture when branch is predicated.
Decode Unit :
There are 2 stage decode : during d1 the opcode is decoded in both the pipelines in order to find whether the 2 instruction can be paired.
If pair is possible both the instruction will be sent for d2 for address of memory resident data calculation.
Control Unit :
This unit predicts the meaning of the instruction & microcode given by the decoder & control the integer unit & floting point unit.
ALU :
This perform arithmetic as well as logical operation.
The ALU is U pipeline can complete an operation prior to ALU in v pipeline.
Address Generator :
Ther are 2 address generators for each pipeline.
Paging Unit :
It translate linear address to physical address.
Floting Point Unit :
Ther are 3 internal units Add, Divide & Multilpy.
That operate simultaneously.