1. Wider data bus width:
- It has 64 bit data bus and 32 bit address bus.
- It allows 8 byte of data info to be transferred to and from memory.
- Bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously.
2. Improved Cache Structure:
- 8KB dedicated instruction cache which gives instruction to its execution units and floating point unit via dual instruction pipeline.
- Cache is organized in a 2 way set associate cache with 32 byte line (256 lines).
- 8KB data cache which gives data to its execution unit.
- This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3. Two parallel integer execution unit:
- It allows the execution of two instructions to be executed simultaneously in a single processor clock.
4. Faster floating point unit:
- The floating point unit has been completely redesigned over 80486.
- Faster algorithms provide up to ten times speed – up for common operations including add, multiply etc.
5. Branch prediction logic:
- The Pentium uses tech called branch prediction.
- To implement this Pentium has two pre-fetch buffers, one to pre-fetch code in linear fashion, and one that pre-fetches code according to the Branch Target Buffer (BTB).
- Therefore, needed code is almost pre-fetched before it is required for execution.
6. Data Integrity and Error Detection:
- The Pentium have added significant data integrity and error detection capability.
- Data parity checking is still byte-by-byte basis.
- Address parity checking has also been added.
7. Functional Redundancy Checking: (provide maximum error detection):
- Two or more Pentium Processor can participate in functional redundancy checking.
- One processor (the master) fetching the instruction and executes the instruction in normal fashion.
- Other processor (the checker) (connected directly to the master processor’s buses)verify correctness of master processor.
- Checker executes the instruction same as the master but doesn’t drive the buses.
- Checker samples master’s output and compares the values with the internal computed values. An error signal is asserted in case if mismatch occurs.
8. Super Scalar Architecture:
- Processor is capable of parallel instruction execution of multiple instructions are known as superscalar processors.
- Pentium is capable in some cases of executing two integer of two floating point instruction simultaneously and thus support superscalar architecture.
Pentium Architecture:
The term ''Pentium processor'' refers to a family of microprocessors that share a common architecture and instruction set. The first Pentium processors were introduced in 1993. It runs at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of Pentium architecture are
- Complex Instruction Set Computer (CISC) architecture with Reduced Instruction Set Computer (RISC) performance.
- 64-Bit Bus
- Upward code compatibility.
- Pentium processor uses Superscalar architecture and hence can issue multiple instructions per cycle.
- Multiple Instruction Issue (MII) capability.
- Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple instructions so that it takes less time to execute two instructions in a row.
- The Pentium processor fetches the branch target instruction before it executes the branch instru
- The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instructions and for data. It allows the Pentium processor to fetch data and instructions from the cache simultaneo
- When data is modified, only the data in the cache is changed. Memory data is changed only when Pentium processor replaces the modified data in the cache with a different set of data
- The Pentium processor has been optimized to run critical instructions in fewer clock cycles than 80486 processor.
