Draw and explain architecture of SUN SPARC

SPARC is an acronym for Scalable Processor ARChitecture
Engineered at Sun Microsystems in 1985
Designed to optimize compilers and pipelined hardware implementations
Offers fast execution rates
SPARCs are load/store RISC processors.
Load/store means only loads and stores access memory directly.
RISC (Reduced Instruction Set Computer) means the architecture is simpliﬁed with a limited number of instruction formats and addressing modes.
Simple, uniform instruction set allowing fast cycle times.
Goal — “One instruction per cycle.”(RISC)
Up to 128 general-purpose registers
All arithmetic operations are register-to-register
Simplified instruction set
Higher number of instructions with fewer transistors
Flexible integration of cache, memory and FPUs
64-bit addressing and 64-bit data bus
Increased bandwidth
Fault tolerance
Nine stage pipeline; can do up to 4 instructions per cycle
On-chip 16Kb data and instruction caches with 2Mb external cache
A large “windowed” register file — at any one instant, a program sees 8 global integer registers plus a 24-register window into a larger register file.

SPARC Architecture

Contains the general purpose registers and controls the overall operation of the processor.
Executes the integer arithmetic instructions and computes memory addresses for loads and stores.
Maintains the program counters and controls instruction execution for the FPU.

When a procedure is called, the register window shifts by sixteen registers, hiding the old input registers and old local registers and making the old output registers the new input registers.
Input registers : arguments are passed to a function
Local registers: to store any local data.
Output registers: When calling a function, the programmer puts his argument in these registers.

The FPU has
32 Registers (32-bit single-precision floating-point registers)
32 Registers (64-bit double-precision floating-point registers)
16 Registers (128-bit quad-precision floating-point registers)
Floating-point load/store instructions are used to move data between the FPU and memory.
The memory address is calculated by the IU.
Floating-Point operate (FPop) instructions perform the floating-point arithmetic operations and comparisons.

The instruction set includes support for a single, implementation-dependent coprocessor.
The coprocessor has its own set of registers.
Coprocessor load/store instructions are used to move data between the coprocessor registers and memory.

Block Diagram Ultra SPARC

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